Stress Probability Computation for Estimating NBTI-Induced Delay Degradation
نویسندگان
چکیده
PMOS stress (ON) probability has a strong impact on circuit timing degradation due to NBTI effect. This paper evaluates how the granularity of stress probability calculation affects NBTI prediction using a state-of-the-art long term prediction model. Experimental evaluations show that the stress probability should be estimated at transistor level to accurately predict the increase in delay, especially when the circuit operation and/or inputs are highly biased. We then devise and evaluate two annotation methods of stress probability to gate-level timing analysis; one guarantees the pessimism desirable for timing analysis and the other aims to obtain the result close to transistor-level timing analysis. Experimental results show that gate-level timing analysis with transistor-level stress probability calculation estimates the increase in delay with 12.6% error. key words: NBTI, stress probability, timing analysis
منابع مشابه
Static Aging Analysis Using 3-Dimensional Delay Library
The growing concern about time-dependent performance variations of CMOS devices due to aging-induced delay degradation has increased with shrinking technology dimensions of the devices . One of the main causes of aging is Negative Bias Temperature Instability (NBTI). Modeling NBTI-induced delay at gate level depends on the real stress activity of gate inputs which are related to the workload ap...
متن کاملبررسی و مدلسازی اثر ناپایداری در دمای بالا و بایاس منفی (NBTI) و تزریق حاملهای پرانرژی (HCI) در افزارههای چندگیتی نانومتری
In this paper, analytical models for NBTI induced degradation in a P-channel triple gate MOSFET and HCI induced degradation in an N-channel bulk FinFET are presented, through solving the Reaction-Diffusion equations multi-dimensionally considering geometry dependence of this framework of equations. The new models are compared to measurement data and gives excellent results. The results interpre...
متن کاملSimulation-Based Analysis For NBTI Degradation In Combinational CMOS VLSI Circuits
The negative-bias temperature instability (NBTI) is one of the dominant aging degradation mechanism in today Very Large Scale Integration (VLSI) Integrated Circuits (IC). With the further decreasing of the transistor dimensions and reduction of supply voltage, the NBTI degradation may become a critical reliability threat. Nevertheless, most of the EDA tools lack in the ability to predict and an...
متن کاملNBTI Mitigation Method by Inputting Random Scan-In Vectors in Standby Time
Negative Bias Temperature Instability (NBTI) is one of the serious concerns for long-term circuit performance degradation. NBTI degrades PMOS transistors under negative bias, whereas they recover once negative bias is removed. In this paper, we propose a mitigation method for NBTI-induced performance degradation that exploits the recovery property by shifting random input sequence through scan ...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید
ثبت ناماگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید
ورودعنوان ژورنال:
- IEICE Transactions
دوره 94-A شماره
صفحات -
تاریخ انتشار 2011